VHDL for logic synthesis (Record no. 20330)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00572nam a22002057a 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20180415152950.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 180415b ||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9780470688472 |
| 041 ## - LANGUAGE CODE | |
| Language code of text/sound track or separate title | eng |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 R896v3 |
| 100 ## - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Rushton, Andrew |
| 245 ## - TITLE STATEMENT | |
| Title | VHDL for logic synthesis |
| Statement of responsibility, etc | Andrew Rushton |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 3rd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | United Kingdom |
| Name of publisher | Wiley |
| Year of publication | 2011 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | xvii, 466p. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | VHDL (Computer hardware description language) |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Logic design |
| General subdivision | Data processing |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Computer-aided design |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Text Book |
| Lost status | Damaged status | Collection code | Home library | Current library | Shelving location | Date acquired | Cost, normal purchase price | Full call number | Accession Number | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|
| Electronic and Communication | Central Library | Central Library | Reference | 15/04/2018 | 6137.92 | 621.395 R896v3 | 15967 | REF |