Digital design (Record no. 22701)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00607nam a22002177a 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200908163547.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 200908b ||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9789353062019 |
| 041 ## - LANGUAGE CODE | |
| Language code of text/sound track or separate title | eng |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815 M317d6 |
| 100 ## - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Mano, M. Morris |
| 245 ## - TITLE STATEMENT | |
| Title | Digital design |
| Remainder of title | with an introduction to the verilog HDL, VHDL and System verilog |
| Statement of responsibility, etc | M. Morris Mano |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 6th ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | Noida |
| Name of publisher | Pearson |
| Year of publication | 2018 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 765p. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Logic design |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Logic circuits |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Digital integrated circuits |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Ciletti, Michael D. |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Text Book |
| Lost status | Damaged status | Collection code | Home library | Current library | Shelving location | Date acquired | Cost, normal purchase price | Full call number | Accession Number | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|
| Computer Science | Central Library | Central Library | General Stacks | 08/09/2020 | 699.00 | 621.3815 M317d6 | 17823 | Text Book |